Method and apparatus for simultaneous recording and displaying two different video programs

ABSTRACT

A method and apparatus for simultaneously recording and displaying video signals from two different video sources. The apparatus comprises a main channel processing circuit/logic ( 148 ), a second channel processing circuit/logic ( 150 ), and common circuitry/logic ( 152 ). The common circuitry comprises a digital video encoder pipe ( 112 ) that decodes both a first and second encoded video signals. The main channel processing circuit processes a first decoded video signal utilizing a first clock to form a main picture for display. The second channel processing circuit processes a second decoded video signal to form a PIP picture for combination with the main picture for display. The PIP picture is produced using a second clock signal that is independent from the first clock signal. In a record mode, the second channel clock is coupled to the second channel processing circuit to produce a recordable signal using a digital encoder. The recordable signal also forms the PIP picture that is coupled to the main channel processing circuit to produce a PIP picture that is used to monitor the recording process.

BACKGROUND OF THE DISCLOSURE

[0001] 1. Field of the Invention

[0002] The invention relates to televisions and, more particularly, theinvention relates to signal processing techniques for simultaneouslyrecording and displaying two video programs.

[0003] 2. Description of the Background Art

[0004] Television viewers have come to desire to simultaneously recordand view programs from two different video sources, e.g., a satellitetelevision program and a standard terrestrial broadcast program.However, various video sources produce video signals that have differenthorizontal and vertical synchronization rates. As such, two separatevideo decoder and display generation systems are used to facilitateviewing one program, while producing an output signal of another programthat can be recorded as well as viewed in a picture-in-picture (PIP)display. Such a system requires the hardware of two televisionreceivers. As such, a television with such a capability is veryexpensive.

[0005] Therefore, a need exists in the art for a television having asingle video decoder system that is capable of displaying a main picturefrom a first video signal plus producing a recordable signal from-asecond video signal as well as producing a PIP picture for monitoringthe recordable signal.

SUMMARY OF THE INVENTION

[0006] The disadvantages associated with the prior art are overcome by amethod and apparatus for simultaneously recording and displaying videosignals from two different video sources. The apparatus comprises a mainchannel processing circuit for a main signal, a second channelprocessing circuit for a second signal, and common circuitry forprocessing both the main and second signals. The common circuitryincludes a digital video variable length pipe and a decode pipe thatdecodes both the main and second digitally encoded (compressed) videosignals.

[0007] The main channel processing circuit processes a main video signalto form a main picture for display. The second channel processingcircuit processes a second video signal that, when selected forrecording also forms a PIP picture for combination with the main picturefor display. The second channel processing circuit also processes themain video signal that, when selected for recording, also forms a PIPpicture for combination with the main picture for display. In thismanner, the PIP forms a record monitor.

[0008] The main decoded video signal or the second decoded video signalis also presented to a record output to which a recorder may be coupledto receive the selected first or second decoded video signal forrecording.

[0009] During the decoding process, the main channel processing circuitand the second channel processing circuit utilize a main clock signalthat is derived from the main signal (the faster of the clocks). Duringrecording either the main clock signal or a second clock signal that isindependent from the main clock signal is utilized to provide clockingfor a record out signal and the record monitor PIP.

[0010] When the main signal is being recorded (and providing a PIP), aVmain signal from a main raster generator is utilize to drive a digitalencoder (DENC) in a Vslave mode for the record out. When the secondsignal is being recorded, the DENC receives a start-up reset in order toread in the second signal vertical rate parameters and the vertical syncis generated by the DENC itself.

[0011] In PIP only-mode (record switch off), the main signal clock isused for the second channel. In the record mode, either the main signalclock or the second signal clock is used depending on whether the sameor different source is being recorded, respectively. In the record mode,the video is sent to the graphics processor for capture and display aswell as forwarded to the DENC for recording. The captured pictures arethen retrieved without additional reformatting for display as a “recordmonitor” PIP image. This PIP image is preferably somewhat larger that astandard PIP image and is also preferably labeled a record monitor PIP.Because the record pictures are being reproduced based on the recordoutput timing, it may be necessary to skip or repeat pictures whenpresented as a PIP overlay on the main signal output.

[0012] In one form, since there is only one VCXO generated referenceclock based on the video decode process, the second signal uses a clockthat is derived from the main signal clock, is but different as needed(for example, 81 MHz for a 60 Hz main, and 27 MHz for a 59.95 Hzrecord). Because the studio clock used for the video of the secondsignal may deviate slightly from the studio clock of the video for thefirst signal, a form of clock recovery is required for the secondsignal. If the second signal video is derived from an analog source,then the buffer level of captured pictures is used as an indication ofwhether the DENC clock is running too fast or too slow. When the secondsignal is digital, then a local counter is sampled based on the arrivaltime of clock reference bearing transport packets. A comparison betweenthe sampled clock and delivered clock reference is used as an indicationof whether the DENC clock is running too fast or too slow. A PLL(Phase-Locked Loop) and programmable divider are used to generate thesecond signal clock, using the main signal recovered time base as therecovered time base as the reference. The PLL divider is altered asnecessary to align the generated clock with the ideal frequency for thesecond signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The teachings of the present invention can be readily understoodby considering the following detailed description in conjunction withthe accompanying drawings, in which:

[0014]FIG. 1 depicts a block diagram of one form of a video processingsystem in accordance with the principles of the present invention;

[0015]FIG. 1A depicts a block diagram of another form of a videoprocessing system in accordance with the principles of the presentinvention;

[0016]FIG. 1B depicts a block diagram of yet another form of a videoprocessing system in accordance with the principles of the presentinvention;

[0017]FIG. 2 depicts a detailed block diagram of a video decoderapparatus utilizable in the systems of FIGS. 1, 1A, and 1B in accordancewith the principles of the present invention;

[0018]FIG. 3 is a table of exemplary clock frequencies that can beprocessed and/or generated by the present invention showing variousresulting parameters; and

[0019]FIG. 4 is a flow chart of an exemplary method in accordance withthe principles of the present invention.

[0020] To facilitate understanding, identical reference numerals havebeen used, where possible, to designate identical elements that arecommon to the figures.

DETAILED DESCRIPTION

[0021] Referring to FIG. 1 there is depicted a block diagram of a videoprocessing system, generally designated 50, operable to receive, decode,record, and/or display a plurality of video signals from different videosources. In particular, the system 50 is principally concerned with thedecoding and/or processing a pair of video signals (video 1 and video 2)that are coupled to the system 50. Each video signal may be an analog ordigital signal. Thus, the term “decoding” as used herein includesprocessing/decoding in the case of an analog signal, anduncompressing/decoding in the case of a digital signal (i.e. a digitallyencoded video signal).

[0022] In the case of a digital signal, the system 50 uses a decoderthat processes a pair of digital signals or alternatively a pair ofdecoders, one for each signal. Further, while any digital encodingformat may be decoded, the present invention will be discussed in termsof signals that have been encoded using the Moving Pictures Expert Group(MPEG) standard. These signals may be supplied by a satellite televisionreceiver, a high definition television (HDTV) receiver, digital cablereceiver, digital cable television system, digital terrestrialtelevision antenna, and the like. In the case of an analog signal, anyanalog format such as NTSC, PAL, SECAM, or the like may be decoded bythe system 50. Thus, while any analog format may be decoded, the presentinvention will be discussed in terms of signals that have been encodedusing the NTSC standard. These signals may be supplied by a televisionreceiver, cable receiver, cable television system, terrestrialtelevision antenna, a television components, and the like.

[0023] The system 50 comprises a decoder apparatus 100 a display 52(e.g., a television, television monitor or the like), and a recorder 58(e.g., a video cassette recorder (VCR), video tape recorder (VTR),digital recorder, or the like). In the system 50, each above referencedcomponent, i.e. the decoder apparatus 100, the display 52, and therecorder 58, are separate components and are coupled to each other bypatch cords or other suitable conductors/connectors. The decoderapparatus 100 decodes both of the video signals using common decodingcircuitry and dual timing circuitry to produce a signal for a mainpicture 54 (e.g., from video 1) and a signal for recording on therecorder 58 as well as for display in a PIP picture 56 of the mainpicture 54 of the display 52. As such, the system 50 simultaneouslyproduces a video signal for display and for recording as well as thecapability to monitor the recordable signal in a PIP picture. By usingcommon circuitry to process two video signals, the decoder apparatus isless expensive to manufacture than prior art decoder apparatus. As well,the present invention utilizes independent clock recovery/generationcircuitry in addition to the common decoding circuitry, to provideclocking for the main video and the record/PIP video.

[0024] Referring to FIG. 1A, there is depicted another form of a videoprocessing system in accordance with the principles of the presentinvention as set forth herein, generally designated 50A, that operatesand/or functions in the same manner as the video processing system 50 ofFIG. 1 of which the operation/function is described in detail below. Thesystem 50A includes the decoder apparatus 100, a display 52 (e.g. atelevision, television monitor or the like), and the recorder 58.However, in the system 50A, the decoder apparatus 100 is integral withthe display 52 as a component 60, while the recorder 58 is a separatecomponent. The recorder 58 is coupled to the integral component 60 by apatch cord or other suitable conductor/connector.

[0025] Referring to FIG. 1B, there is depicted yet another form of avideo processing of a video processing system in accordance with theprinciples of the present invention as set forth herein, generallydesignated 50B, that operates and/or functions in the same manner as thevideo processing system 50 of FIG. 1 of which the operation/function isdescribed in detail below. The system 50B includes the decoder apparatus100, a display 52 (e.g. a television, television monitor or the like),and the recorder 58. However, in the system 50B, the decoder apparatus100 is integral with the recorder 58 as a component 70, while thedisplay 52 is a separate component. The display 52 is coupled to theintegral component 70 by a patch cord or other suitableconductor/connector.

[0026] Referring now to FIG. 2, there is depicted a detailed blockdiagram of the decoder apparatus 100 of FIGS. 1, 1A, and 1B. The decoderapparatus 100 comprises main channel processing circuitry/logic 148,second channel processing circuitry/logic 150, and commoncircuitry/logic 152. The main channel processing circuitry/logic 148 iscoupled to a main channel in port 102 such that the main channelprocessing circuitry/logic 148 receives a main channel or signal,typically from a main tuner (not shown). The second channel processingcircuitry/logic 150 is coupled to a second channel in port 104 such thatthe second channel processing circuitry/logic 150 receives a secondchannel or signal, typically from a second tuner (not shown). However,as explained below, the second channel processing circuitry/logic 150may receive the main signal as a “second channel” for processing whenthe main signal is selected for recording rather than the second signal.

[0027] The main signal or generally, main data, is provided to a MainData Input to a main channel memory buffer 106, part of the main channelprocessing circuitry/logic 148. The main signal may be a digital signalor an analog signal, and may constitute video and/or audio. It should beappreciated, however, that the present invention is principallyconcerned with video and thus the present invention will be discussed interms of video only. Additionally, the main (video) signal typicallyconstitutes a single channel previously discriminated via the main tuner(not shown) from a plurality of channels.

[0028] When the main signal is analog, the main signal is provided to aFIFO (First In First Out) memory or buffer 108. When the main signal isdigital, the main signal is provided to an MPEG video VLD (VariableLength Decoder) pipe 110 that decodes the variable length coding of theMPEG signals. The variable length decoded main signal is then providedto an MPEG video decode pipe 112. The MPEG video decode pipe 112 isoperable to decode the MPEG coding of the variable length decoded mainsignal. In accordance with MPEG principles, the MPEG video decode pipe112 stores decoded MPEG frames of the main signal in the main channelmemory buffer 106. The MPEG video decode pipe 112 utilizes some of thepreviously decoded MPEG frames of the main signal for motioncompensation and the like in decoding incoming MPEG main signals fromthe MPEG video VLD pipe 110, thus the two-headed arrow between the MPEGvideo decode pipe 112 and the main channel memory buffer 106. Thedecoded MPEG frames of the main signal are stored in a correct orderback in the main channel memory buffer 106.

[0029] The second signal is provided to a PIP/Record Input to a secondchannel memory buffer 114, part of the second channel processingcircuitry/logic 150. The second signal may be a digital signal or ananalog signal, and may constitute video and/or audio. It should beappreciated, however, that the present invention is principallyconcerned with video and thus the present invention will be discussed interms of video only. Additionally, the second (video) signal typicallyconstitutes a single channel previously discriminated via the secondtuner (not shown) from a plurality of channels.

[0030] When the second signal is analog, the second signal is providedto a FIFO (First In First Out) memory or buffer 116. When the secondsignal is digital, the second signal is provided to the MPEG video VLD(Variable Length Decoder) pipe 110 that decodes the variable lengthcoding of the MPEG signals. The variable length decoded second signal isthen provided to the MPEG video decode pipe 112. The MPEG video. decodepipe 112 is operable to decode the MPEG coding of the variable lengthdecoded second signal. In accordance with MPEG principles, the MPEGvideo decode pipe 112 stores decoded MPEG frames of the second signal inthe second channel memory buffer 114. The MPEG video decode pipe 112utilizes some of the previously decoded frames of the second signal formotion compensation and the like in decoding incoming MPEG secondsignals from the MPEG video VLD pipe 110, thus the two-headed arrowbetween the MPEG video decode pipe 112 and the second channel memorybuffer 114. The decoded MPEG frames of the second signal are stored in acorrect order back in the second channel memory buffer 114.

[0031] The MPEG video VLD pipe 110 is part of the common circuitry/logic152 and performs the variable length decoding of the main signal and thesecond signal in an interleaved manner to enable a single VLD decoder toperform variable length decoding of the two video signals (i.e. the mainsignal and the second signal).

[0032] The MPEG video decode pipe 112 is also part of the commoncircuitry/logic 152 and performs the MPEG video decoding of the mainsignal and the second signal. Using an interleaving process, the MPEGvideo decode pipe 112 decodes both of the video signals and returns thedecoded video frames to the respective buffers 106 and 114. Since theMPEG video decode pipe 112 is shared by the two video signals, thefaster of the two decode rates is used to decode both of the signals,i.e., a 60 Hz decode rate is used over a 59.94 decode rate. If bothvideo signals have the same decode rate, then, of course, the MPEG videodecode pipe 112 uses the decode rate of the two signals. In the casewhere the decode rates are different, the slower input video stream isprocessed faster than necessary. As such, the decoding process for theslower stream will occasionally stop to ensure that a data underflowcondition will not occur in the compressed data buffer (buffer 106 or114).

[0033] The MPEG video decode pipe 112 couples the signal (e.g., video 1)that will form the main picture to the main channel memory buffer 106and couples the signal (e.g., video 2) that will form the PIP pictureand be recorded to the second channel memory buffer 114. The selectionof which signal is the main picture and which is the PIP picture isgenerally accomplished by a viewer through a remote control or otherwell-known interface (not shown).

[0034] The buffer 106 and the buffer 114 are coupled to respective FirstIn First Out (FIFO) memories 108 and 116. The access (read and write)process of both of the FIFO buffers 108 and 116 is controlled by asingle clock generator 122. The clock generator 122 produces a clocksignal to each FIFO buffer 108 and 116 that is derived from a clocksignal that is produced by a reference clock generator 124. The clocksignal produced by the reference clock generator 124 is locked to themain channel timing signal.

[0035] The output of the FIFO memory buffer 108 is provided to an inputof main channel format converters 118 that are clocked by the clocksignal-from the clock generator 122. The output of the FIFO memorybuffer 116 is provided to an input of PIP/Record channel formatconverters 134 that are clocked by the clock signal from the clockgenerator 122. The format converters 134 are labeled as “PIP/Recordchannel” format converters because the second channel/signal is notalways the channel/signal that is being recorded and hence would not beprovided as a PIP. When the main channel/signal is chosen for recording,the main channel/signal is provided as a PIP.

[0036] The output of each of the converters 118 and 134 is coupled to arespective FIFO memory 120 and 136. These FIFOs buffer the video framesof the respective signals to ensure that the frames are synchronizedwith the display timing signals. Access to the FIFO 120 is controlled bythe reference clock from the main channel locked reference clockgenerator 124. Access to the FIFO 136 is controlled by either thereference clock from the main channel locked reference clock generator124 in the case of the main channel being selected for recording, or asecond clock from a second channel clock generator 132 in the case ofthe second channel/signal being selected for recording. The secondchannel clock generator 132 is keyed to the second channel/signal.

[0037] The reference clock signal from the reference clock generator 124is also coupled to the main raster generator 138. The main rastergenerator 138 produces the horizontal (H) and vertical (V)synchronization signals that facilitate display of the main picture ontoa cathode ray tube or liquid crystal display. The H and V signals arecoupled to a display generator 126 for controlling the raster scan ofthe pixel data. The pixel data to the display generator 126 comes fromthe FIFO memory 120 (i.e. the main channel/signal) and the FIFO memory136 (i.e. either the second channel/signal or the main channel/signal,depending on which channel/signal is selected for recording).

[0038] Additionally, the display generator 126 produces the on screengraphics that can be recalled from the graphics memory 128 and controlsthe insertion of the PIP picture into the main picture. The display,comprising on-screen graphics, PIP picture and main picture, is coupledto the main digital-to-analog converters (DACs) 130 that produce ananalog display for viewing on a television screen via a display out portor output.

[0039] The main raster generator 138 also provides a Vmain signal to asecond channel controller 140. The second channel controller 140 also isoperable to receive a Vsecond signal from a microprocessor (μP) 144,microcontroller or the like. The second channel controller 140 outputseither the Vmain signal to a digital-to-NTSC encoder 142 or a Vstart-up(reset) signal in response to the receipt of the Vsecond signal from themicroprocessor 144 to the digital-to-NTSC encoder 142, depending onwhich channel/signal (i.e. the main channel/signal or the secondchannel/signal) is selected for recording. In accordance with an aspectof the present invention, when the main channel/signal is selected forrecording (and thus is provided as a record monitor PIP) the Vmainvertical sync signals are provided through the second channel controller140 to the digital-to-NTSC encoder 142, and when the secondchannel/signal is selected for recording (and thus is provided as arecord monitor PIP) the Vsecond signal triggers the Vstart-up signalwhich causes the digital-to-NTSC encoder 142 to internally generate thevertical sync signals based on the incoming/second clock and/or framerate of the second channel/signal.

[0040] Depending on whether the second channel/signal or the mainchannel/signal is selected for recording, the clocking signal for theFIFO memory 136 is controlled through a switch 146. In accordance withan aspect of the present invention, when the second channel/signal isselected for recording, the second channel/signal provided at the port104 is processed by the second channel processing circuitry/logic 150or/and the common circuitry/logic 152 and provided to the FIFO memory136. The switch 146 is caused to select the second clock signal from thesecond channel clock generator 132 to supply the second clock signal tothe FIFO memory 136. The FIFO memory 136 receives frames from the secondchannel/signal from the PIP/Record channel format converters 134. Therate at which the frames are sent to the FIFO memory 136 from thePIP/Record channel format converters 134 is controlled by thedigital-to-NTSC encoder.142 as indicated by the dashed line between thetwo circuitry/logic blocks. The digital-to-NTSC encoder 142 is alsoclocked by the second clock signal from the second clock generator 132.The label “Record” between the FIFO memory 136 and the digital-to-NTSCencoder 142 indicates that the record signal is going to thedigital-to-NTSC encoder 142. The label “PIP” indicates that the signalis going to the display generator 126 and the graphics memory 128 foroutput to the main DACs 130 for display as a PIP. At the same time thesecond signal from the FIFO memory 136 is provided to the graphicsgenerator 126 and the graphics memory 128 and outputted via the mainDACs 130 to the display out for display on the display (not shown).

[0041] In accordance with another aspect of the present invention, whenthe main channel/signal is selected for recording, the main processedsignal from the main channel memory buffer 106 is caused to be providedto the second channel memory buffer 114 and through the appropriatecomponents to the FIFO memory 136. The FIFO memory 136 is caused to beclocked by the main channel clock from the main channel locked referenceclock generator 124 via the switch 146. At the same time, Vmain isprovided through the second channel controller 140 to thedigital-to-NTSC encoder 142 to provide the vertical sync pulses for themain channel/signal. As well, the digital-to-NTSC encoder 142 receivesthe main clock signal from the main clock generator 124. The mainchannel/signal from the FIFO memory 136 is also provided to the displaygenerator 126 and the graphics memory 128 for output as a PIP on thedisplay.

[0042] In accordance with the principles presented herein, reference isnow made to generally designated FIG. 3. In FIG. 3, there is depicted achart or table, of various exemplary clock frequencies that aregenerated or produced by the main channel reference clock generator andthe second channel reference clock generator to facilitate the output ofvideo signals when their sources may or may not have slightlydifferencing crystal reference clocks. The various clock frequencies areused by the various components in the manner as described herein.

[0043] Operation

[0044] Referring to FIG. 4, there is depicted a flow chart generallydesignated 160, setting forth an exemplary embodiment of a manner ofoperation of the present invention in accordance with the principlespresented herein. It should be initially understood that the orderand/or sequence of the manner of operation shown in the flowchart 160 ischangeable. As well, all of the steps shown and/or described may or maynot be necessary for the operation thereof.

[0045] A main channel or signal is received, block 162. As well, asecond channel or signal is received, block 164. Thereafter, both themain channel/signal and the second channel/signal are processed, block166. The main channel/signal is provided to the display as a mainpicture utilizing a main clock signal derived from the mainchannel/signal, block 168. A channel/signal (either the mainchannel/signal or the second channel/signal) is selected for recording,block 170. If the main channel is selected for recording, the mainchannel is provided as a PIP in the main picture and at a Record Outport or output utilizing the main clock, block 172. If the secondchannel is selected for recording, the second channel is provided as aPIP in the main picture and at the Record Out port or output utilizing asecond clock that is derived independent from the main clock, block 174.

[0046] Although various embodiments that incorporate the teachings ofthe present invention have been shown and described in detail herein,those skilled in the art can readily devise many other variedembodiments that still incorporate these teachings.

1. A method of viewing a first video signal and a second video signalthat is to be recorded comprising the steps of: (a) decoding a firstvideo signal using a first clock reference (b) decoding a second videosignal using said first clock signal; (c) providing the first decodedvideo signal to a display as a main picture using the first clocksignal; and (d) providing the second decoded video signal to the displayas a PIP in the main picture and to a record out port using a secondclock signal.
 2. The method of claim 1, wherein the steps of decodingthe first video signal and decoding the second video signal areperformed by a common video decoder.
 3. The method of claim 1, whereinthe first and second video signals are digitally encoded.
 4. The methodof claim 3, wherein the steps of decoding the first video signal anddecoding the second video signal are performed by a common video decoderpipe that is operable to decode video signals encoded in a movingpictures expert group (MPEG) format.
 5. A method of providing a recordmonitor on a display comprising the steps of: (a) decoding a first videosignal using a first clock signal; (b) decoding a second video signalusing the first clock signal; (c) providing the first-decoded videosignal as a main picture to a display using the first clock signal; and(d) providing the second decoded video signal to the display as a PIP inthe main picture using a second clock when the second video signal isselected for recording, else providing the first decoded video signal tothe display as a PIP in the main picture using the first clock when thefirst video signal is selected for recording.
 6. The method of claim 5,wherein the steps of decoding the first video signal and decoding thesecond video signal are performed by a common video decoder.
 7. Themethod of claim 5, wherein the first and second video signals aredigitally encoded.
 8. The method of claim 7, wherein the steps ofdecoding the first video signal and decoding the second video signal areperformed by a common video decoder pipe that is operable to decodevideo signals encoded in a moving pictures expert group (MPEG) format.9. An apparatus for monitoring the recording of a video signalcomprising: a video decoder pipe operable to decode encoded first andsecond video signals; a first channel processing circuit coupled to saidvideo decoder pipe and operable to produce a main picture from the firstdecoded video signal for display using a first clock signal; a secondchannel processing circuit coupled to said video decoder pipe andoperable to produce a second decoded video signal; selection means forselecting either the first video signal for recording or the secondvideo signal for recording; and means for providing the second decodedvideo signal as a PIP for display in the main picture using a secondclock signal when the second video signal is selected for recording, andfor providing the first decoded video signal to the display as a PIP inthe main picture using the first clock when the first video signal isselected for recording.
 10. The apparatus of claim 9, furthercomprising: a reference clock generator coupled to said first channelprocessing circuit and said second channel processing circuit andoperable to produce the first clock signal; and a second channel clockgenerator coupled to said means for providing and operable to provide asecond clock to the second decoded video signal when the second videosignal is selected for recording.
 11. The apparatus of claim 9, furthercomprising a digital encoder to produce an analog signal for recording.12. The apparatus of claim 11, wherein said digital encoder produces aninternal vertical synchronization signal when the second video signal isselected for recording, else the digital encoder is operable to receivean externally generated vertical synchronization signal when the firstvideo signal is selected for recording.
 13. The apparatus of claim 12,further comprising a vertical synchronization signal generator operableto produce an externally generated vertical synchronization signal basedon the first video signal.
 14. The apparatus of claim 9, wherein saidvideo decoder pipe is operable to decode video signals encoded in amoving pictures expert group (MPEG) format.